Category Archives: vhdl

FPGA used VHDL for Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You can see a video of the results, below.

The FPGA board is a ZestSC1 that has a relatively old Xilinx Spartan 3 chip onboard. Still, it is plenty powerful enough for a task like this.

The project doesn’t directly drive a display. It does the math, stores the results in the board’s onboard RAM and then sends a frame to the PC using the …read more

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Posted in fpga, fractal, mandelbrot, vhdl, xilinx, zestsc1 | Leave a comment

VexRISC-V Exposed

If you want to use FPGAs, you’ll almost always use an HDL like Verilog or VHDL. These are layers of abstraction just like using, say, a C compiler is to machine language or assembly code. There are other challenges to the throne such as SpinalHDL which have small but enthusiastic followings. [Tom] has a post about how the VexRISC-V CPU leverages SpinalHDL to make an extremely flexible system that is as efficient as plain Verilog. He says the example really shows off why you should be using SpinaHDL.

Like a conventional programming language, it is easy to find niche languages …read more

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Posted in fpga, RISC-V, spinalhdl, verilog, vexrisc-v, vhdl | Leave a comment

Apple II FPGA

[Stephen Edwards] had some time one Christmas. So he took a DE2 FPGA board and using VHDL built a pretty faithful reproduction of an Apple II+ computer. He took advantage of VHDL modules for the 6502 CPU and PS/2 keyboard, and focused more on the video hardware and disk emulation.

According to [Stephen], you can think of the Apple II as a video display that happens to have a computer in it. The master clock is a multiple of the color burst frequency, and the timing was all geared around video generation. [Stephen’s] implementation mimics the timing, although using more …read more

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VexRiscv: A Modular RISC-V Implementation for FPGA

Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.

SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.

When you build a CPU in FPGA, …read more

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Printer Scrap Becomes FPGA Devboard

These days, if you want to start learning about FPGAs, it can be a daunting experience. There’s a huge variety of different platforms and devboards and it can be difficult to know where to start. [RoGeorge] decided to take a different tack. Like a 16-year-old drag racer, he decided to run what he brung – a printer control panel cum FPGA development board (Romanian, get your Google Translate on).

[RoGeorge] was lucky enough to score a couple of seemingly defective control panels from HP Laserjets discarded by his workplace. Seeing potentially good parts going to waste, like keypads and LCDs, …read more

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Posted in HP, laserjet, printer, vhdl | Leave a comment